Implementing electronic circuits involves connecting isolated devices through specific electronic paths. In silicon integrated circuit fabrication it is necessary to isolate devices, which are built into the same silicon matrix, from one another. They are subsequently interconnected to create the desired circuit configuration. In the continuing trend toward higher device densities, parasitic inter-device currents become more problematic. Isolation technology has thus become one of the most critical aspects of contemporary integrated circuit fabrication.
Over the last few decades a variety of successful isolation technologies have been developed to address the requirements of different integrated circuit devices, such as NMOS, CMOS and bipolar. In general, the various isolation technologies exhibit different attributes with respect to such characteristics as minimum isolation spacing, surface planarity, process complexity and the defect density generated during isolation processing. Moreover, it is common to trade off some of these characteristics when developing an isolation process for a particular integrated circuit application.
In metal-oxide-semiconductor (MOS) technology it is necessary to provide an isolation structure that prevents parasitic channel formation between adjacent devices, such devices being primarily NMOS or PMOS transistors or CMOS circuits. The most widely used isolation technology for MOS circuits has been that of LOCOS isolation, an acronym for LOCal Oxidation of Silicon. LOCOS isolation essentially involves the growth of recessed or semirecessed silicon dioxide (SiO.sub.2 or oxide) in unmasked nonactive or field regions of the silicon substrate, producing the so-called field oxide (FOX). The masked regions of the substrate generally define active areas (AA) within which devices are subsequently fabricated. The FOX is generally grown thick enough to lower any parasitic capacitance occurring over these regions, but not so thick as to cause step coverage problems. The great success of LOCOS isolation technology is to a large extent attributed to its inherent simplicity in MOS process integration, cost effectiveness and adaptability.
An exemplary prior art LOCOS isolation process is illustrated in FIGS. 1-2. As shown in FIG. 1, a silicon substrate 20 is typically masked by a so-called masking stack 26 comprising a pad-oxide layer 22 and a masking nitride layer 24 (Si.sub.3 N.sub.4). The masking stack 26 is typically patterned by conventional photolithographic means and etched to expose selected regions of the silicon substrate 20 for FOX growth. As shown in FIG. 2, an exemplary active area array 30 is defined and protected from oxide growth by the patterned masking stack segments 32. Field isolation of the active areas is achieved by growing FOX in the unmasked portions of the silicon substrate. After FOX growth, the masking stack segments 32 are removed and devices are fabricated within the active areas.
In spite of its success, several limitations of LOCOS technology have driven the development of improved or alternative isolation structures. As further shown in FIG. 2, active area features 36, defined by the resulting FOX growth, often differ from the intended structure 38 because of nonideal effects present in conventional LOCOS processing. For example, light diffraction and interference around photolithographic mask edges during the patterning process typically produces rounding at mask comers, an effect which is exacerbated in small features such as found in DRAM active area arrays 30. Additionally, isolated, narrow photolithographic features such as shown here are often susceptible to lifting and nonuniformities due to mask misalignment.
A major limitation in LOCOS isolation is that of oxide undergrowth or encroachment at the edge of the masking stack which defines the active regions of the substrate. This so-called bird's beak (as it appears) poses a serious limitation to device density, since that portion of the oxide adversely influences device performance while not significantly contributing to device isolation. Furthermore, as IC device density increases, the undesirable effects of bird's beak growth become particularly problematic for active area features in the sub half-micron regime. The bird's beak encroachment becomes particularly severe at narrow, terminating features 38 as shown in FIG. 2. A cross-section 2A--2A of the FOX structure, shown in FIG. 2A, illustrates the deleterious effects of bird's beak encroachment. As shown in FIG. 2A, FOX regions 31 may extend beneath a substantial portion of mask regions 33 near the end or terminating portion of an active area. As mentioned earlier, near the terminus of narrow features, the encroachment becomes particularly severe, often severely distorting the AA feature and causing masking stack lifting.
Unfortunately, various techniques augmenting the basic LOCOS process are often accompanied by undesirable side effects or undue process complexity. For example, in DRAM fabrication technology, conventional LOCOS processes are often scaled for smaller device dimensions by increasing the nitride thickness and reducing the pad oxide thickness to reduce the FOX encroachment. This also increases stress in the nitride as well as the underlying silicon, creating crystal defects which increase device junction leakage. On the other hand, if the nitride stack is not increased, stack lifting causes unpredictable changes in the shape of the active areas, particularly at the terminus of small features typically found in DRAM applications.
In the continuing trend toward higher density and higher performance integrated circuits, effective field isolation on a submicron scale remains one of the most difficult challenges facing current process technology. While conventional LOCOS processes have sufficed in the past, there remains a critical need for improved field isolation.